Vortex Release (August 4, 2025)

Release notes- August 4 2025

August 4

Vortex Release Version (August 4, 2025)

  • Card-not-present transactions processed via Vortex Stripe ACS now include the security code (CVC) in the authorization request to Stripe, enhancing fraud prevention. For failed attempts, the totalAmount is preserved, and the Stripe payment intent ID is returned as a reference number to support improved traceability and issue resolution.

  • Incremental authorization support was added, enabling merchants to increase the authorized amount on existing payment intents prior to final capture. This allows for flexible handling of variable transaction totals without initiating new authorizations.

  • Stripe Terminal now supports refund handling for Interac cards. Refunds require both card and customer presence and are processed by capturing refund.created and refund.failed events. These events are published to the card payment topic in Vortex, using Stripe response data to generate accurate return transactions.

  • Overcapture functionality is now supported for Stripe Payment API transactions. Authorized transactions can be completed for an amount greater than the original authorization, subject to validation rules. Overcapture is only permitted before any funds are received, and the system enforces a single final capture. Additional fields like overcaptureAmount and authorizedAmount were introduced for transparency across authorization and capture flows.

  • A discrepancy involving AMEX sale transactions was corrected, where certain transactions appeared "Declined" in the MXM App but were marked "Approved" in the Vortex database. The fix ensures accurate synchronization of transaction statuses, especially during delayed or timeout scenarios, by triggering reversals where appropriate.

  • Checkout now supports Level 3 data for Visa transactions, including detailed product descriptions at the line-item level. These enhancements support Visa’s March 2025 interchange optimization program by using MCC-driven mappings to apply eligible product descriptions, helping merchants qualify for reduced rates.

  • Corrected a formatting error in the AMEX additional detail record within the Fiserv Omaha Tap Trans file. The 6A record now correctly uses "C" in the 80th byte when followed by 6G (Retail) or 6R (Restaurant) records, resolving certification rejections during settlement testing.

  • Enhanced compliance for AMEX lodging transactions in the Omaha Tap Trans settlement file. Updates include correct population of the 80th byte in the 5 Detail record, exclusion of unnecessary 6A records, proper ordering of 6L records, and accurate lodging-specific field values. These changes align lodging data with certification standards and prevent future file rejections.

  • Settlement file generation for MasterCard transactions was enhanced by including the Acceptor URL address. For FD North PTS, the Acceptor URL is now placed into the XM06 record. For TSYS, it is populated in Field 28 (positions 209–238) of the EXTG2 record. These updates ensure accurate settlement formatting and alignment with MasterCard authorization data.

  • Memory configuration for the Emitter service was updated and added to orchestration to ensure consistency across deployments. This prevents future overwrites during releases and improves resource reliability in production environments.

Impact

This release introduces critical enhancements across Vortex payment flows, improving flexibility, traceability, and compliance. Merchants can now leverage incremental auth and overcapture to better manage complex or evolving payments, while support for Interac refunds and AMEX lodging ensures regional and vertical-specific compatibility. Improved data handling, including Level 3 Visa descriptions and Stripe CVC inclusion, enhances fraud prevention, interchange optimization, and system visibility. Backend improvements, such as file formatting corrections and memory orchestration updates, reinforce platform stability and certification readiness across networks and processors.

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